The present invention relates generally to the field of microprocessor to peripheral interfacing, and more particularly to a universal bus interface circuit for use in conjunction with a requesting microprocessor using bus control that can be either synchronous or asynchronous with respect to the microprocessor clock and a peripheral device having a clock that is not synchronized with the microprocessor clock.
Microprocessor applications requiring a host or requesting microprocessor to be interfaced with a peripheral processing device are prevalent. In such applications, the peripheral device is typically programmed to carry out input/output operations and/or data processing separately from the host microprocessor. Consequently, such a peripheral device may contain its own microprocessor, input/output circuitry, clock and control circuitry, and different addressable memory locations.
In such applications, it is not always desirable to synchronize the peripheral clock with the clock in the host microprocessor, so the peripheral clock can run at any speed relative to the microprocessor clock (either faster or slower). As a result of the difference between the peripheral and host microprocessor clocks, as well as the architecture and particular type of memory units employed in the peripheral device, the access time for different addressable memory locations within the peripheral can vary.
For a host microprocessor to access (i.e., write data to and read data from) memory locations within the above described general peripheral processing device, an interfacing circuit is required for coupling the microprocessor and peripheral address and data buses, and to provide the appropriate timing for data transfers. Since conventional microprocessors operate using either synchronous or asynchronous bus control, separate bus interfacing circuits have generally been required when interfacing a peripheral device with microprocessors that use the two types of bus control.
Consequently, there exists a need for a generic bus interface circuit for interfacing a microprocessor having either synchronous or asynchronous bus control with a processing peripheral device, where the microprocessor and peripheral can have different asynchronous clocks, and peripheral memory locations accessible to the microprocessor can have different access times.